al Analysis of the sion Limits of ~ ~ e t a l ~ n ~ erconnect under ration Current Pulses

Thermal analysis of the fusion limits of the IC metal under short duration current pulses has been performed using a quadruple level TiNiAICulTiN metallization system. A finite element (FE) simulation program has been calibrated to analyze the thermal effects in detail, The program can be used to predict self heating under DC and transient current conditions for various metal levels, geometries and current loading conditions. It is shown both experimentally and using FE simulations that the metal temperatures rise past 1000 OC before open circuit failure under short duration current pulses. The critical failure current is strongly influenced by the metal thickness, thermal capacity and pulse width. Further, it is shown that the ratio of the critical energy causing open circuit conditions (fusion limit), to the theoretical melt energy increases with scaling. As a result, narrower metal lines can sustain higher current densities before failure. Introduction Aggressive scaling of Si based IC devices motivated by the desire for faster speed and higher packing density has increased the functional complexity of VLSI circuits. This has in turn, reduced the metal pitch and increased the number of metallization levels. Recently it has been demonstrated that thermal effects, instead of electromigration (EM) itself will start to dominate interconnect design guidelines for advanced high performance interconnects [ 1,2]. Further, metal interconnects get heavily stressed due to high joule heating in field programmable gate arrays (FPGA) [3] wherein the interconnect metal is exposed to short duration, high current pulses. Also, metal heating and failure caused by short time current pulses as encountered during ESDEOS testing and radiation testing for latchup has become a reliability issue [4]. It is desirable to comprehend the fusion limits of the interconnect under such current pulses since IC interconnects will soon encounter this limit as the ultimate limit of their scalability. We have recently presented a model for interconnect heating and failure under pulsed current stress [SI. The purpose of this paper is to extend our previous work, using experimental data and finite element simulations, to comprehend the implications of fusion limits of the IC metal under a short duration current pulse and to study the effect of interconnect scaling on this limit. Experimentsminite Element Model The test samples used in the experiments were prepared in a quadruple level metallization (QLM) wafer process. The test structures, were isolated, i.e. there were no metal layers on top of another. A 2-D finite element model was set up to describe the cross section in detail (Fig. 1). Fig. 1 also shows the 3-D model which has been generated to consider a cell of densely packed array structures including the case of lines crossing at different levels, as an example for real circuits. In both models it is possible to select ar,y of the metallization levels and lines to be included in the actual simulation test. level level Level level 4 3 2 I